Integrated injection logic (I.sup.2 L) circuits operate at a relatively low signal level of one volt. Significant problems have confronted the prior art in attempting to achieve signal communication between separate I.sup.2 L chips because of this low signal level. Auxiliary voltage boosting circuits at the chip I/O require a higher voltage breakdown characteristic in the base-collector junction of the vertical bipolar device used in the off chip driver (OCD). But increasing the base-collector thickness in the downward injecting, vertical bipolar OCD causes the upward injecting vertical bipolar transistor used in the internal I.sup.2 L logic circuits to have a poor emitter efficiency and a large charge storage characteristic, since both devices must be made simultaneously in any practical, economic fabrication process. Thus existing practical I.sup.2 L circuits face the dilemma of either having fast internal logic circuitry and low voltage OCDs or slower internal logic circuitry and higher voltage OCD's.